1. Field of the Invention
The present invention relates generally to reconfigurable computing platforms.
2. Description of the Prior Art
The electronic industry currently faces the challenge of designing high performance embedded systems called Systems-on-a-Chip. Specialized hardware circuits called processor array architectures are an important option for implementing such systems. In most previous techniques for designing array architectures, the processors did not fully exploit the possibility of on-chip memory and runtime hardware reconfiguration. These features are becoming more critical to the electronic industry. However, current technologies do not fully exploit these features and operate inefficiently with large slowdown in execution times.
An example of such a current restrictive technology is a systolic array. Systolic Arrays are application-specific architectures proposed by Kung and Leiserson 25 years ago for direct very large scale integration (VLSI) implementation of programs. A systolic array consists of a (possibly virtual) grid of simple, non-programmable processing elements (PEs) each with a few registers of local storage and connected to its nearest neighbors. Although they are elegant, and systematic methods for automatically designing systolic arrays from high level programs are now available, they have some serious limitations. For example, the constraints on locality and regularity are too restrictive for modern VLSI circuits. Judiciously designed long wires are thus common in most ASICs. Furthermore, systolic arrays constrain the PEs to have only a fixed number of registers, but current technology allows custom memory blocks to be distributed throughout the circuit. Also, only a small, proper subset of loop programs may be compiled to systolic arrays.